Power MOSFET semiconductor devices having a trench gate have recently been applied to a wide range of various types of power supply devices such as DC-DC converters. An example of this type of semiconductor device is shown in FIGS. 38A and 38B. FIGS. 38A and 38B are explanatory views showing an example of a semiconductor device having the constitution of a power MOSFET pertaining to the prior art, with 38A being a view showing an example of a semiconductor device having a gate trench, and 38B being a view showing an example of a semiconductor device having a gate trench and a source trench. In the figures, reference symbol 111 indicates a N+-type silicon substrate, 112 indicates a N−-type epitaxial layer, 113 indicates a P-type body layer, 114 and 143 indicate source trenches, 115 indicates an N+-type source region, 116 indicates a gate insulating film, 117 indicates a gate electrode film, 119 indicates a source electrode film, 120 indicates a gate trench, 121 indicates a P+-type diffusion region, 125 indicates a drain electrode film, 126 indicates an insulating film, 140 and 142 indicate buried P+-type diffusion regions, and 141 indicates an insulating film.
As shown, for example, in FIG. 38A, a semiconductor device like that described above forms a drain layer in the form of N−-type epitaxial layer 112 on N+-type silicon substrate 111, and forms P-type body layer 113 on N−-type epitaxial layer 112. P+-type diffusion region 121 and N+-type source region 115 are formed within P-type body region 113. P+-type diffusion region 121 and N+-type source region 115 comprise a single cell. A large number of such cells are formed, and are arranged in the form of a lattice or staggered lattice in a planar constitution. Alternatively, P+-type diffusion region 121 and N+-type source region 115 are formed into a striped pattern by continuing the cross-sectional structure shown in FIG. 38A.
Moreover, gate trench 120 is formed extending to N−-type epitaxial layer 112 through P-type body layer 113. Gate insulating film 116 is formed and closely adhered to the top surface and bottom surface of gate trench 120, and gate electrode film 117 is formed in the space surrounded by gate insulating film 116. In addition, insulating film 126 is formed so as to cover gate insulating film 116 and gate electrode film 117, and a separate insulating film 141 is formed on the surface of N+-type source region 115 and insulating film 126.
Moreover, source electrode film 119 is formed on insulating film 141 and P+-type diffusion region 121, and on a portion of N+-type source region 115. In addition, drain electrode film 125 is formed on the other side of N+-type silicon substrate 111.
In this semiconductor device, when a voltage is applied between source electrode film 119 and drain electrode film 125, and a voltage greater than or equal to a predetermined threshold value is applied between gate electrode film 117 and source electrode film 119, an inversion layer is formed in the boundary region with gate insulating film 116 of P-type body layer 113 that serves as a channel. Current then flows through this channel from drain electrode film 125 to source electrode film 119.
However, in a semiconductor device having this type of constitution, in the case of attempting to reduce the size of the device, it is necessary to make the cell size smaller by reducing mesa width E. Therefore, the structure shown in FIG. 38B is known as a way to reduce cell size. Namely, a source trench 114 is formed within the cell, and a source electrode film 119 is formed within source trench 114. Moreover, a structure is also known in which, after injecting impurities such as boron in the vicinity of the bottom of source trench 114, those impurities are heated and diffused to form buried P+-type diffusion region 140. According to this structure, as a result of a portion of source electrode film 119 being buried in source trench 114, mesa width F can be made to be smaller than mesa width E of FIG. 38A.
However, when cell size is made considerably smaller, due to limitations on the accuracy of the photographic step of trench formation, the source trench is not formed at a predetermined location, but rather as indicated for source trench 143, for example, is frequently formed in close proximity to gate trench 120. In such cases, when a certain degree of variation occurs in the diffusion range of buried P+-type diffusion region 140, there is diffusion to the extent to contact gate insulating film 116 as indicated for buried P+-type diffusion region 142. Since buried P+-type diffusion region 142 ends up being formed so as to be interposed P-type body layer 113 and N+-type source region 115, a shift occurs in the predetermined threshold value previously mentioned.
In order to solve the aforementioned problems, an object of the present invention is to provide a semiconductor device capable of preventing a buried diffusion region formed near the bottom surface of a source trench from diffusing to the extent that it contacts a gate trench in the vicinity of that buried diffusion region even in the case the accuracy of the photographic step of trench formation is not that high.